Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology

Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology, the second of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Third Edition, thoroughly examines real-time logic (RTL) to GDSII generation, analog/mixed-signal design, physical verification, and technology computer-aided design (TCAD). Chapters contributed by leading experts authoritatively discuss design for manufacturability (DFM) at the nanoscale, power supply network design and analysis, design modeling, and much more. New to This Edition: - Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs - Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography - New coverage of cutting-edge applications and approaches realized in the decade since the publication of the second edition-these are illustrated by updates including the impact of new analog layout methods, chiplet integration, and power-optimized design, in various chapters Offering improved depth and modernity, this book provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.

Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley in 1992 and from Politecnico di Torino in 1993. He co-authored two books on asynchronous circuit design, a book on hardware/software co-design of embedded systems, and over 250 scientific papers. Between 1993 and 2000 he was the architect of the POLIS project, a cooperation between U.C. Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a complete hardware/software co-design environment for control-dominated embedded systems. Between 2003 and 2014 he was one of the creators and architects of the Cadence CtoSilicon high-level synthesis system. Since 2011, Dr. Lavagno has been a full professor with Politecnico di Torino, Italy. He has served on the technical committees of several international conferences in his field (e.g. DAC, DATE, ICCAD, ICCD, ASYNC, CODES) as well as various workshops and symposia and is a senior member of IEEE. He has also been an associate editor of IEEE TCAS and ACM TECS. His research interests include the high-level synthesis of digital circuits and the acceleration of Machine learning algorithms using Field Programmable Gate Arrays. Grant E. Martin retired from his position as a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA, in 2023. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor's and master's degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at several major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001 and was co-chair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is a senior member of IEEE. Although retired, he continues to have an interest in system-level design, IP-based design of system-on-chip, platform-based design, DSP, baseband and image processing, and embedded software.

Section 1. RTL to GDS-II, or Synthesis, Place, and Route. 1. Design Flows. 2. Logic Synthesis. 3. Power Analysis and Optimization from Circuit to Register Transfer Levels. 4. Equivalence Checking. 5. Digital Layout. 6. Static Timing Analysis. 7. Structured Digital Design. 8. Routing. 9. Physical Design for 3D Ics. 10. Gate Sizing. 11. Clock Design and Synthesis. 12. Exploring Challenges of Libraries for Electronic Design. 13. Design Closure. 14. Tools for Chip-Package Codesign. 15. Design Databases. 16. FPGA Synthesis and Physical Design. Section 2. Analog and Mixed-Signal Design. 17. Simulation of Analog and RF Circuits and Systems. 18. Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits. 19. Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip. Section 3. Physical Verification. 20. Design Rule Checking. 21. Resolution Enhancement Techniques and Mask Data Preparation. 22. Design for Manufacturability in the Nanometer Era. 23. Design and Analysis of Power Supply Networks. 24. Noise in Digital Ics. 25. Layout Extraction. 26. Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation. Section 4. Technology Computer-Aided Design. 27. Process Simulation. 28. Device Modeling: From Physics to Electrical Parameter Extraction. 29. High-Accuracy Parasitic Extraction.