High k Gate Dielectrics

The drive toward smaller and smaller electronic componentry has huge implications for the materials currently being used. As quantum mechanical effects begin to dominate, conventional materials will be unable to function at scales much smaller than those in current use. For this reason, new materials with higher electrical permittivity will be requ

Michel Houssa Laboratoire Materiaux et Microelectronique de Provence, Universite de Provence, France Silicon Processing and Device Technology Division, IMEC, Belgium

Introduction The need for high-k gate dielectrics and materials requirement Deposition techniques ALCVD, MOCVD, PLD, MBE Characterization Physico-chemical characterization X-ray and electron spectroscopies Oxygen diffusion and thermal stability Defect characterization by ESR Band alignment determined by photo-injection Electrical characteristics Theory of defects in high-k materials Bonding constraints and defect formation at Si/high-k interfaces Band alignment calculations Electron mobility at the Si/high-k interface Model for defect generation during electrical stress Technological aspects Device integration issues Device concepts for sub-100 nm CMOS technologies Transistor characteristics Nonvolatile memories based on high-k ferroelectric layers